The invention relates to a DRAM cell configuration, that is, to an array of memory cells with dynamic random access, and to a method for producing the configuration.
For a memory cell of a DRAM cell configuration, at present almost exclusively a so-called one-transistor memory cell is used, which includes one transistor and one capacitor. The information in the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, so that when the transistor is triggered via a word line, the charge of the capacitor can be read out via a bit line.
The general goal is to create a DRAM cell configuration that has a high packing density.
U.S. Pat. No. 5,208,657 describes a DRAM cell configuration in which a memory cell includes a transistor and a capacitor. To increase the packing density, the transistor is disposed on four flanks of an indentation in which a memory node of the capacitor is disposed. The indentation is disposed below a region in which a word line and a bit line of the memory cell intersect. The transistor is embodied as a vertical transistor, and its gate electrode is disposed in the indentation above the memory node. The space required for the memory cell is at least 6.25 F, where F is the minimum feature size feasible in the production technology employed.
The object of the present invention is to provide a DRAM cell configuration and a production method which overcome the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and whereby the invention provides for a DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties compared with the prior art, without having to reduce the packing density of the DRAM cell configuration. It is a further object to provide for a method for producing such a DRAM cell configuration.
With the above and other objects in view there is provided, in accordance with the invention, a DRAM cell configuration, comprising:
a substrate and memory cells each including at least one vertical transistor and one capacitor, a first indentation and a second indentation;
said first indentation and said second indentation being laterally offset from one another, with said second indentation of a first memory cell adjoining said first indentation of an adjacent, second memory cell and adjoining said substrate;
an upper source/drain region, a channel region, and a lower source/drain region of said transistor being disposed in said substrate, one above the other, and each adjoining a first flank of said first indentation and adjoining said second indentation;
a capacitor dielectric of said capacitor formed on at least a portion of said first flank of said first indentation, said dielectric having a recess formed therein in a region of said lower source/drain region of said transistor, and wherein a bottom of said second indentation is located lower than a lower edge of said recess;
said capacitor having a memory node disposed in said first indentation, and said node in said recess adjoining said lower source/drain region of said transistor;
said transistor having a gate electrode disposed in said second indentation; and
a word line connected to said gate electrode of said transistor of said memory cell, and a bit line extending transversely to said word line and connected to said upper source/drain region.
In other words, the objects of the invention are attained by a DRAM cell configuration which has memory cells that each include at least one vertical transistor and one capacitor. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed one above the other, and each adjoins both a first flank of the first indentation and the second indentation. At least a portion of the first flank of the first indentation is provided with a capacitor dielectric of the capacitor, which dielectric has a recess in the region of the lower source/drain region of the transistor. A memory node of the capacitor is disposed in the first indentation, and in the recess this node adjoins the lower source/drain region. A gate electrode of the transistor is disposed in the second indentation.
The memory cells are connected to word lines and to bit lines that extend transversely to the word lines.
The object is also attained by a method for producing a DRAM cell configuration, in which memory cells are created, which each have one vertical transistor and one capacitor. As parts of the transistor in the substrate, a lower source/drain region, a channel region, and an upper source/drain region are created, so that they are disposed one above the other. In the substrate, a first indentation is created, which with a first flank adjoins the lower source/drain region, the channel region, and the upper source/drain region. The first indentation is provided with a capacitor dielectric of the capacitor. The capacitor dielectric is provided with a recess on the first flank of the first indentation, in the region of the lower source/drain region. In the first indentation, a memory node of the capacitor is created, which in the recess adjoins the lower source/drain region. A second indentation is created that adjoins the upper source/drain region, the channel region, and the lower source/drain region. A gate electrode of the transistor is created in the second indentation. Word lines and bit lines, which extend transversely to the word lines, are created and connected to the memory cells.
The second indentation of the memory cell is located outside the first indentation of the memory cell.
The DRAM cell configuration can have a high packing density, since the transistor is designed as a vertical transistor, the memory node is disposed in an indentation, and a connection between the memory nodes and the lower source/drain region is made possible by means of a recess of the capacitor dielectric, which requires no additional space.
The quality of a boundary layer of the channel region, where a gate dielectric of the transistor is created, generally has a great influence on electrical properties of the transistor. It is consequently advantageous to produce this boundary layer with special care. In comparison to U.S. Pat. No. 5,208,657, the transistor can be produced with improved electrical properties, since different indentations are provided for the capacitor and for the transistor, and so the boundary layer of the channel region can remain spared from process steps for creating the first indentation.
The provision of two different indentations furthermore offers the advantage that the geometry of the boundary layer of the channel region can be independent of any geometry of a face at which the capacitor dielectric is created. The boundary layer of the channel region is preferably flat, so that it has a defined orientation with regard to the crystal lattice of the substrate, so that the gate dielectric can grow homogeneously. The face in which the capacitor dielectric is created is conversely preferably curved, so that the capacitor dielectric has no edges where field distortions could lead to leakage currents. Both the transistor and the capacitor can have especially good electrical properties.
A horizontal cross section through the first indentation is circular or elliptical, for instance.
To increase the packing density, it is advantageous if the first indentations and the second indentations of the memory cells are disposed such that the second indentation of a first one of the memory cells adjoins the memory node which is disposed in the first indentation of a second one of the memory cells. The memory cells are immediately adjacent one another or overlap.
To simplify the process, it is advantageous if the memory node is created at least at first such that at least also at a second flank of the first indentation, which flank is opposite the first flank of the first indentation, in the region of a further recess, it adjoins the substrate.
The capacitor dielectric is deposited essentially conformally, for instance after the first indentation has been created, so that faces of the first indentation are covered without the first indentation being filled. Next, the first indentation is filled with conductive material. The conductive material is etched back to a lower level. Next, exposed parts of the capacitor dielectric are removed. By deposition of further conductive material, the first indentation is re-filled. Next, the conductive material is back-etched to an upper level, which is located above the lower level. In this way, not only is the recess of the capacitor dielectric created at the first flank of the first indentation between the lower level and the upper level, but the further recess of the capacitor dielectric is in particular also created at the second flank of the first indentation. If the first indentation with further flanks between the upper level and the lower level adjoins the substrate, then recesses are created at these flanks as well. The memory node is created from the conductive material.
The conductive material is for example doped silicon.
A further possible way of creating the memory node is, after deposition of the capacitor dielectric, to fill the first indentation with conductive material and to etch the conductive material back to the upper level. Next, by isotropic etching, exposed parts of the capacitor dielectric and parts of the capacitor dielectric that are disposed between the upper level and the lower level are removed. By deposition and back-etching of further conductive material, a gap between the conductive material and the substrate is filled. As the further conductive material, amorphous doped silicon is especially suitable, because it can be conformally deposited well and causes no defects in the adjoining substrate.
To create the lower source/drain region, a tempering step is performed, in which at least in the region of the recess, dopant from the memory node diffuses into the substrate.
Alternatively, the lower source/drain region is created by structuring a doped layer of the substrate.
A middle layer, doped by a first conductivity type, can be disposed between two layers doped with a second conductivity type that is opposite the first conductivity type. The layers can be created by in situ doped epitaxy or by implantation. The channel region is created from the middle layer, and the upper source/drain region and the lower source/drain region are created from the other layers. This has the advantage that a channel length of the transistor can be set precisely, since the process precision with regard to the thickness of the layers, especially in epitaxy, is low. If an implantation is performed, this can also be done after the indentations have been created.
To reduce leakage currents, it is advantageous if a low-doped part of the lower source/drain region is created by structuring the doped layer, and if a highly doped part of the lower source/drain region is created by diffusion of dopant out of the memory node. The low-doped part surrounds the highly doped part in such a way that the highly doped part does not adjoin either the substrate or the channel region. This kind of DRAM cell configuration has soft p-n junctions and consequently less leakage current, since only the low-doped part of the lower source/drain region adjoins the channel region and the substrate.
It is within the scope of the invention if the highly doped part does adjoin the channel region but not the substrate, or does adjoin the substrate but not the channel region.
To increase the packing density, it is advantageous if the memory node at the second flank of the first indentation does not adjoin the substrate. This makes it possible to lessen a spacing between adjacent first indentations without causing leakage currents between the associated memory nodes.
To create this kind of memory node, it is within the scope of the invention to prevent the embodiment of the further recess, by applying a mask that covers the second flank before the exposed parts of the capacitor dielectric are removed.
To simplify the process, it is advantageous by comparison if the memory node is first created such that it also adjoins the substrate at the second flank of the first indentation. The second indentation is created such that its bottom is located lower than a lower edge of the recess. At the second flank of the first indentation of the second memory cell, the second indentation separates the memory node of the second memory cell from the substrate. Consequently the creation of a mask to prevent the further recess can be dispensed with, and at the same time a high packing density is attained.
If the spacing between the first indentations is small, then doped regions created in the out-diffusion can grow together, so that the lower source/drain region is created in the form of a layer that at first extends from the first indentation of the first memory cell to the first indentation of the second memory cell. By the creation of the second indentation, the lower source/drain region is structured such that it no longer adjoins the first indentation of the second memory cell and thus no longer adjoins the memory node of the second memory cell.
It is advantageous if an upper face of the memory node is located in the region of the recess, that is, at its upper edge, and if an insulating structure is disposed in the first indentation on the memory node.
Since the memory node does not extend higher, or for instance does not extend as far as a surface of the substrate, a capacitance between the memory node and the upper source/drain region or the channel region or the lower source/drain region of the transistor is avoided. Furthermore, the insulating structure makes it possible to reduce the size of a boundary face between the memory node of the second memory cell and the second indentation of the first memory cell, so that a capacitance between the gate electrode of the first memory cell, or a word line that is disposed partly in the second indentation of the first memory cell, and the memory node of the second memory cell is decreased. This is especially advantageous whenever the second indentation is provided with a gate dielectric before the gate electrode is created; otherwise, no additional, thicker insulating structure that reduces the capacitance is provided on relatively large parts of the boundary face in the second indentation.
It is advantageous if the second indentation of the first memory cell is laterally offset from the first indentation of the second memory cell, so that the second indentation of the first memory cell is disposed partly in the first indentation of the second memory cell and partly in the substrate. A width of the insulating structure is at least large enough that triggering of the transistor of the second memory cell by the gate electrode of the first memory cell and/or by the word line, which is located partly in the second indentation of the first memory cell, is prevented. As a result of the overlap of the two memory cells, the DRAM cell configuration can be produced with a high packing density. Both the first indentation and the second indentation can be created with masks, which have a width of only F, where F is the minimum feature size feasible in the technology employed. A spacing between first indentations can amount to F. A spacing between the second indentation and the first indentation of the same memory cell can be less than F.
With the above and other objects in view there is also provided, in accordance with the invention, a method of producing a DRAM cell configuration as outline above, comprising:
forming a first indentation and a second indentation in a substrate, with the first indentation and the second indentation laterally offset from one another;
forming memory cells, each with a vertical transistor and a capacitor, and wherein the second indentation of a first memory cell adjoins the first indentation of an adjacent second memory cell and adjoins the substrate;
forming transistors in the substrate, with a lower source/drain region, a channel region, and an upper source/drain region disposed one above the other;
wherein the first indentation is formed in the substrate such that a first flank of the first indentation adjoins the lower source/drain region, the channel region, and the upper source/drain region;
forming a capacitor dielectric of a capacitor in the first indentation;
providing the capacitor dielectric with a recess on the first flank of the first indentation, in a region of the lower source/drain region;
creating a memory node of the capacitor in the first indentation, wherein the node in the recess adjoins the lower source/drain region;
wherein the second indentation is formed to adjoin the upper source/drain region, the channel region, and the lower source/drain region, and a bottom of the second indentation is located lower than a lower edge of the recess;
forming a gate electrode of the transistor in the second indentation;
creating a word line and a bit line extending transversely to the word line; and
connecting the gate electrode of the transistor to the word line, and connecting the upper source/drain region to the bit line.
In other words, to create this kind of DRAM cell configuration, first at least the channel region and the lower source/drain region of the transistor of the first memory cell can be created such that before the second indentation of the first memory cell is created, they adjoin the first indentation of the first memory cell and the first indentation of the second memory cell. After the capacitor dielectric is created and the conductive material is deposited, a mask is created, which is disposed above the first flanks of the first indentations but does not cover regions above the second flanks of the first indentations. The second indentation is created with the aid of a mask, and both at least the substrate and the conductive material are etched. The conductive material is structured by means of the second indentation, creating the memory node. It is within the scope of the invention if before the second indentation is created, the upper source/drain region also adjoins the first indentation of the first memory cell and the first indentation of the second memory cell.
It is within the scope of the invention if the second indentation of the first memory cell is disposed in the substrate and outside the first indentation of the second memory cell and adjoins the second flank of the first indentation of the second memory cell. To that end, in the creation of the second indentation with the aid of a mask which is disposed above the first flanks of the first indentations, the substrate is etched.
In this case, in the finished DRAM cell configuration as well, the capacitor dielectric can have the further recess, so that the second indentation of the first memory cell adjoins the memory node of the second memory cell in the region of the further recess.
For creating such a DRAM cell configuration, first a mask can be created that covers the first indentations that are to be created. Between the first indentations that are to be created, trenches are created by making spacers at flanks of the mask, and the substrate is etched selectively to the mask and to the spacers. The trenches are filled with insulating material. Next, material is deposited and back-etched, so that the material is located between parts of the mask. The mask is removed, and the first indentations are created by etching the substrate selectively to the material. The substrate is covered with the insulating material. A portion of the substrate that adjoins the first flank of the first indentation of the first memory cell is exposed. The substrate is etched isotropically, and the trench filled with the insulating material acts as a lateral etch stop, so that in the substrate, a recess is created which adjoins the first flank of the first indentation of the first memory cell. The recess is filled with insulating material. The insulating material and the insulating structure are partly replaced by the mask for the second indentations, in that the insulating material and the insulating structure are back-etched and material is deposited and planarized, until a portion of the substrate is exposed that adjoins the second flank of the first indentation of the second memory cell and adjoins the trenches. The second indentations are created with the aid of this mask, by etching the substrate selectively to the material. An especially advantageous aspect of this method is that elongation of the substrate perpendicular to the plane of the channel can be adjusted precisely even if a spacing between adjacent first indentations amounts to no more than F. This elongation determines the threshold voltage of the transistor. In this case, it is defined by the width of the spacers, since the trenches are created between adjacent spacers, and since by acting as an etch stop the trenches determine how large a region covered by the mask for the second indentations is.
It is within the scope of the invention if the second indentation of the first memory cell is disposed in the first indentation of the second memory cell and together with the first indentation of the second memory cell shares a portion of the second flank of the first indentation of the second memory cell. In that case, the elongation of the substrate perpendicular to the plane of the channel is determined by a first mask, which is used to create the first indentations.
In a first possible way of creating a DRAM cell configuration of this kind, a first layer is placed on the substrate and structured in accordance with the first indentations. After the insulating structure has been created, a second layer is placed and structured such that it is disposed above the first flanks of the first indentations and does not cover the regions above second flanks, opposite the first flanks, of the first indentations. The first layer and the second layer act as a mask in the creation of the second indentations, in which the insulating structure and the conductive material begin to be etched. The first layer and the second layer comprise a material which can be etched selectively to the insulating structure. If the insulating structure is of SiO2, then the first layer and the second layer can for instance comprise silicon nitride. It is advantageous if on the first layer, a layer that can be etched selectively to the second layer is created. On that layer, the second layer is created. The layer can act as an etch stop in the structuring of the second layer, so that the first layer is not attacked.
In a second possible way of creating a DRAM cell configuration of this kind, a layer is placed on the substrate and structured in accordance with the first indentations. Spacers are created at the first flanks of the first indentations. The second indentations are created by etching the conductive material selectively to the layer and the spacers. The spacers can be the insulating structures. Alternatively, the spacers are removed and replaced by the insulating structures. In both cases, a width of the second indentations is determined by the thickness of the spacers.
To enable reducing a minimum capacitance of the capacitor that is required because of background noise to read out the information from the memory cell, it is advantageous if the DRAM cell configuration has so-called folded bit lines. In folded bit lines, the signal of the bit line by way of which the information is read out is compared with the signal of a bit line, adjacent to the bit line, whose signal comprises background noise. In this way, the background noise can be filtered out. To assure that the signal of the adjacent bit line will comprise only background noise, no memory cell that is connected to the adjacent bit line can be allowed to be connected to the word line with which the memory cell to be read out is connected.
To make a DRAM cell configuration with folded bit lines possible with a high packing density at the same time, it is advantageous if the second indentation is part of a word line trench in which two different word lines are disposed. The gate electrode of the transistor is part of one of the word lines. To create the word lines, conductive material can be deposited and back-etched, creating the word lines in the form of spacers at the flanks of the word line trench. In this case it is especially advantageous if, as described above, the second indentation is disposed partly in the substrate and partly in the first indentation, since the second indentation can have a width of at least F and can simultaneously have a high packing density, so that there is sufficient space for the two word lines in the same word line trench.
To simplify the process, it is advantageous if only a single word line is disposed in the word line trench. In that case, the term used is xe2x80x9copen bit lines.xe2x80x9d
To create a capacitor electrode of the capacitor, before the memory node is created a dopant source can be created in the first indentation, from which dopant diffuses into the substrate in a tempering step. The capacitor electrode is a doped region in the substrate and surrounds at least part of the first indentation. Arsenic glass, for instance, is suitable as a dopant source; it is deposited in such a way that faces of the first indentations are covered, but the first indentations are not filled. Next, the first indentations are filled with a polymer, such as photoresist, which is etched back to a level that is located below the level of the lower source/drain regions to be created. Next, exposed arsenic glass is removed. By means of a tempering step, arsenic diffuses out of the arsenic glass into the substrate. If a spacing between adjacent first indentations is sufficiently small, then adjacent capacitor electrodes grow together and form one common capacitor electrode.
The capacitor electrode can also be created by plasma immersion. In that process, ions of a plasma diffuse into the substrate. The common capacitor electrode can also be created as a doped layer of the substrate, before the first indentation is created. This layer is created for instance by epitaxy or by implantation.
If the lower source/drain region is created by diffusion of dopant, for instance out of the memory node, or by structuring of a doped layer of the substrate, and if word line trenches are provided, then it is advantageous if the upper source/drain region, at least part of the channel region, and the insulating structure are disposed in the direction of the word lines between two insulators. This prevents a word line in the word line trench of the first memory cell from triggering the transistor of the second memory cell, in the region of flanks of the first indentation that adjoin the first flank of the first indentation. The insulators prevent the upper source/drain region from adjoining the word line trench. The upper source/drain region, the channel region, and the lower source/drain region are disposed in the direction of the bit lines between the first indentation and the second indentation.
If the dopant source is used in the creation of the capacitor electrode, then it is advantageous for the insulators to be created after the memory nodes have been created, so that the insulators are not attacked when the dopant source is removed. To that end, after the first indentation is created, insulation trenches are created, which extend substantially parallel to one another and to the bit lines. The first indentation is intersected by two of the insulation trenches, which are adjacent to one another. To that end, both the substrate and material in the first indentation, such as the insulating structure, are etched. The intersecting of the first indentation assures that there is no left-over substrate is between one of the insulators and the first indentation. The transistor of the second memory cell is disposed exclusively at the first flank of the first indentation of the second memory cell and cannot be triggered by a word line of the second indentation of the first memory cell. The insulation trenches are filled with the insulators by deposition of insulating material. Next, word line trenches extending substantially parallel to one another are created, by etching at least both the substrate and the insulators.
The insulating structures can be created either before, after, or together with the insulators.
To increase the packing density, it is advantageous if a spacing between the two insulators amounts to F. To assure that the two insulators will intersect the first indentation despite imprecisions in the calibration of the insulators, a dimension of the first indentation parallel to the spacing between the two insulators amounts to more than F.
To increase the packing density, it is advantageous first to create the insulators and then to create the first indentation.
To assure that there is no substrate between the first indentation and the insulators, the first indentation is preferably created in self-calibrated fashion adjoining the insulators. To that end, with the aid of a striplike mask, whose strips extend transversely to the insulation trenches, the substrate is etched selectively to the insulators. In that case, a dimension of the first indentation parallel to the spacing between the insulators can amount to F. To prevent the insulators from being attacked by removal of the dopant source that is used to create the capacitor electrode, the capacitor so electrode is preferably not produced by out-diffusion.
To prevent leakage currents between adjacent lower source/drain regions of the transistors, it is advantageous if bottoms of the insulation trenches are located lower than the lower source/drain regions. As a result, the lower source/drain region is defined on two sides by the insulation trenches and on the other two sides by the first indentation and the second indentation, respectively. The same is true for the channel region, which is consequently a floating body. Since the gate electrode at one flank of the second indentation is preferably disposed only in the region of the channel region, it is expedient if the word line trench is shallower than the insulation trenches.
To simplify the process, it is advantageous if only a single word line is disposed in each of the word line trenches.
The word line can protrude from the word line trench. This is advantageous, since parts of the word line disposed outside the word line trench can be created from metal, so that the word line has an increased electrical conductivity. Furthermore, such a word line can be structured together with gate electrodes of transistors on the periphery of the DRAM cell configuration, which simplifies the process. For creating such a word line, after the word line trenches have been created at least one conductive material, such as doped polysilicon, is deposited, then structured with the aid of a striplike mask, whose strips extend substantially parallel to the word line trenches and do not cover at least some parts of the word line trenches.
To prevent the substrate from being attacked in the structuring, it is advantageous if a protective layer, created for instance in the creation of the gate dielectric, and which acts as an etch stop, is disposed on the substrate.
To increase the electrical conductivity of the word line, before the conductive material is structured a material having a high electrical conductivity, such as a metal or a metal silicide, can be deposited on the conductive material and then structured together with the conductive material.
If the bit lines are created such that they extend above the word lines, then to avoid short circuits between the bit lines and the word lines, it is advantageous to encapsulate the word lines. To that end, an insulating material, such as silicon nitride, is deposited and back-etched, so that protective spacers are created at flanks of the protruding parts of the word line. The word line can also be covered from above with insulating material, in that before the conductive material of the word line is structured, the insulating material is deposited and structured together with the conductive material. Interstices between the word lines can be filled with an insulating layer in order to create a planar surface. To create contact holes for the bit lines, the insulating layer is etched selectively to the insulating material with the aid of a mask that does not cover regions above the upper source/drain regions. Since the word lines are encapsulated by the insulating material, the DRAM cell configuration can be created with a high packing density. Any slight malalignment of the mask does not cause a short circuit of the word lines by the bit lines. Contacts are created in the contact holes. The contacts and the bit lines are created by depositing conductive material and structuring it with the aid of a striplike mask, whose strips extend transversely to the word lines and at least partly do not cover the contacts.
To avoid topology problems in the production process that an overly high aspect ratio would cause, that is, a ratio of level to width of a feature, it is advantageous for the word lines not to protrude from the word line trenches. For instance, the word lines are created, after the creation of the word line trenches, by depositing conductive material such as doped polysilicon to fill the word line trenches, and then back-etching it until the conductive material outside the word line trenches is removed.
It is within the scope of the invention if the first indentations are disposed such that memory nodes, which adjoin the word line trench, of adjacent memory cells alternatingly adjoin a first flank and a second flank of the word line trench. If a first word line adjoins the first flank of the word line trench and a second word line adjoins the second flank of the word line trench, then the DRAM cell configuration has folded bit lines. The first word line is connected to only every other one of these memory cells. The second word line is connected to the remaining ones of these memory cells, so that memory cells that are connected to adjacent bit lines are not connected to the same word line.
If the insulation trenches are created after the first indentations have been created, then a memory cell of the DRAM cell configuration can have a space requirement of 5 to 6 F2.
It is within the scope of the invention if the first indentations are disposed such that memory nodes, which adjoin the word line trench, of adjacent memory cells adjoin the same flank of the word line trench. A spacing between adjacent word lines and a spacing between adjacent bit lines can be F, so that an effective space requirement per memory cell can amount to 4 F2.
To reduce a capacitance between the word line and the substrate, it is advantageous to dispose an insulating structure which is thicker than the gate dielectric between the word line and the bottom of the word line trench.
It is within the scope of the invention if no word line trenches are provided for the word lines, so that the word lines have excrescences, which are disposed in the second indentations.
It is within the scope of the invention if the word line is disposed in the second indentation of the first memory cell and in the second indentation of the second memory cell.
The substrate is preferably a semiconductor substrate which includes monocrystalline silicon and/or germanium. The substrate can contain GaAs. The substrate can include epitaxially grown layers of semiconductor material.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a dram cell configuration, and method for producing it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.